Coulomb potential

The file stores no coefficients. Before it emits any gate, the script recomputes the table that the lookup loads later. Each entry is one line: a slope s with two fractional bits and an 18-bit intercept g whose leading one is implicit.

The assertion records that every leaf sits at depth seven. The table therefore holds 128 lines, one per lookup address. Inside build_tables, the script also checks the fit exhaustively over every attainable squared distance from 4 upward.

For distinct points r_i, r_j on a 256³ grid, the circuit adds an approximation of round(2²⁴/‖r_i − r_j‖) to a 25-bit accumulator. It declares seven registers in the grader's order: three 8-bit coordinates for each point, then k. These 73 qubits carry input and output; every other qubit starts and ends in |0⟩.

Each coordinate of r_i becomes |r_i,c − r_j,c|. A complement subtraction writes the sign onto one of three sign qubits. A conditional complement and an increment then form the magnitude. The sign qubits keep enough information to restore r_i during the reverse pass. radd is a ripple adder with temporary AND carries.

For an 8-bit magnitude d, d² = Σ_i d_i4ⁱ + Σ_i<j d_id_j2^i+j+1, and every term has a known column. The terms form four groups with at most one term per column. Each group is then a sparse integer that one ripple addition adds into the 18-bit word n2b. No register holds a single square, and no separate summation runs.

Three coordinates give twelve groups. The first group seeds the empty word without an adder. The other eleven follow SQ_SCHED, an order that a dynamic program chose. Each addition stops at the highest bit the partial sum can reach. This order uses 135 adder ANDs; the axis-at-a-time order uses 141 under the same rule.

Writing n₂ = 2^eu with 1 ≤ u < 2 gives 1/√n₂ = 2^−e/2 u^−1/2. The table then follows one curve on [1, 2), and the power of two returns as a shift at the end.

Four rows test whether the top 8, 4, 2, and 1 bits of n2b are zero. An AND ladder forms the flag, and one CX records it in ereg. A row of controlled swaps then shifts the word in place. The four flags encode both the shift and its parity, so no exponent register exists. The shift caps at 15, which normalizes every n₂ ≥ 4.

The address is the exponent parity and mantissa bits 16 to 11: seven bits, 128 slots. The walk descends a binary tree with one AND per internal node; walk_root splits the root with a CX parity wire instead. On this tree the walk costs 126 ANDs.

At each leaf, load_leaf copies the 17 stored intercept bits and the slope onto sreg and slope under the path flag. Mantissa bits 10 to 5 stay outside the address and form the six-bit local coordinate. A seven-bit coordinate that shared its top bit with the address would need 91 lookup ANDs. The disjoint choice costs 35 more, and in exchange it removes one product row on both passes, narrows the slope and the product by one bit each, and lowers the peak by two qubits.

The line value is g − Σ ⌊s·2ⁱ/4⌋ over the set coordinate bits b_i. Row 0 lands as fresh ANDs, and rows 1 to 5 are controlled in-place additions into an 11-bit product. Six controlled additions take the place of a general multiplication. The bound _acc proves that each carry-out target is still zero.

The subtraction complements sreg around two chunked additions: an 8-bit low chunk and a 9-bit high chunk. The borrow wire bq1 stays live through the accumulation, and the mirror erases it; an early erase would compute the borrow twice. The register then widens, and the implicit leading bit is set.

The shift cap sends n₂ = 1, 2, 3 to three recognizable mantissa patterns. Their top mantissa bit is clear, and bits 15 and 16 tell them apart. Two temporary ANDs select XOR corrections that rewrite the intercept to the required pre-shift value.

Three rows of controlled swaps apply the variable shift that restores the scale 2^−e/2. An ancilla-free ripple adder (Cuccaro et al., 2004) then adds the value into k. The first discarded bit, sreg[1], enters as the carry-in, which rounds to nearest. The X pair on n2b[17] adds 2²³ on the small-input branch.

A temporary-AND carry chain would use fewer Toffolis here. It would keep about 23 carry ANDs live while the circuit sits at its 142-qubit peak with no spare width, so the circuit uses the ancilla-free adder.

b.mirror emits the exact inverse of the code between two checkpoints. Segment mirrors undo the shift, the patch, the subtraction, and the product rows in reverse order. After the product rows, slope and sreg again hold exactly the looked-up words, a function of the still-live address.

A reversed lookup would repeat all 126 ANDs. Instead, the circuit measures each word bit in the X basis (Berry et al., 2019). The measurement costs no Toffolis and resets the wire to |0⟩. It leaves the sign (−1)^{⟨y, word(a)⟩} on address a, where y holds the outcomes.

The repair splits the address into three high bits and four low bits. Under each high prefix, the sixteen low-bit signs form a truth table. gamma applies the Möbius transform at build time and rewrites each table as an XOR of Reed–Muller monomials. Each coefficient is an XOR of measurement outcomes, which costs nothing.

A monomial bank forms every product of two or more low address bits: six pairs, four triples, and one quadruple, for 11 Toffolis. The single bits are the address wires themselves. The repair walk reuses the forward walker but stops at depth three, for six path ANDs.

At each depth-three flag, repair_leaf applies Z or CZ gates conditioned on the coefficient bits. These phase gates are free, so 6 + 11 = 17 Toffolis repay the whole unlookup. Corrections below depth three change only free gates, so the repair does not grow with the number of leaves.

The bank is released by measurement. The last three mirrors undo normalization, the squarer, and the differences. They return ereg, n2b, and the sign qubits to |0⟩ and restore r_i.